The present invention relates to a digital PLL circuit that generates a synchronous clock from data recorded in, particularly, a disc recording medium, an information readout device using the digital PLL circuit, a disc readout device using the information readout device, and a signal processing method using the digital PLL circuit.
In recent years, with rapid spread of digital cameras, digital versatile disc (DVD) players, and DVD recorders, it is normal for individuals to record or reproduce large volumes of digital data including not only music data but also video data. For the purpose of saving video information, inexpensive recording media such as a DVD-R/+R have been spread, and such recording media enables reproduction by a DVD player after recording. In recent years, the DVD players have been being increasingly replaced with Blu-ray disc (BD) players that enable mass recording and reproduction.
An information reproduction technology of an optical disc device will be described. Concentric or spiral guide grooves (tracks) are formed in an optical disc medium, and countless fine information pits are formed along the tracks. The optical disc device irradiates an optical disc medium recording surface that is rotated by a spindle motor with a condensed laser beam. In this situation, focusing servo is so performed as to keep a constant distance between the optical disc surface and a beam condensing objective lens. Also, a tracking servo is performed in a radial direction of the optical disc so that the condensed beam follows the tracks. As a result, the fine information pits formed on the optical disc are accurately scanned with the condensed beam. The presence or absence of the information pits can be detected as contrasting or polarization of the condensed beam reflected light, and detected as a reproduced radio frequency (RF) signal, that is, an electric signal by a photodetector. The condensed beam diameter depends on a laser wavelength and an objective lens numeral aperture (NA), and is also finite. For that reason, an intersymbol interference occurs, and the frequency characteristics of the reproduced RF signal become a low pass filter (LET) characteristics in which a high-pass gain is deteriorated. Under the circumstances, after passing through a filter that allows the high-pass gain to be boosted, the synchronous clock is extracted by a phase locked loop (PLL), and the RF signal is identified as digital data in timing of the synchronous clock. Thereafter, after demodulation using a run length limited (RLL) code, or an error correction using an error correction code (ECC) has been conducted, the data is extracted as the music information or the video information. During recording, conversely, an ECC parity is added to user information, 8/16 modulation is conducted, and information to which a specific code has been added on a frame basis is recorded on the optical disc in synchronism with a recording clock. A meandering component is detected by the guide groove that meanders at a constant frequency in a radial direction, and the detected component is multiplied to generate the recording clock. The detected meandering component is called “wobble signal”. A laser power is increased at a position to be recorded to increase a temperature of the condensed portion, and the physics are changed reversibly or irreversibly to form the fine information pits.
Incidentally, as a method for controlling the rotation of the disc recording medium such as an optical disc, there are mainly two types of systems described below. That is, there are a constant linear velocity (CLV) control system that keeps a constant linear velocity, and a constant angular velocity (CAV) control system that keeps a constant rotating angular velocity. In the CAV control, a torque of a spindle motor can be reduced, and power consumption is also suppressed. On the other hand, a ratio of the linear velocity between the inner and outer peripheries is about 2.4 times, and in a capture frequency range of the PLL by which the synchronous clock is extracted from the readout signal, when it is assumed that the frequency range of the inner periphery is 1, there is a need to cover the range of from 1 to 2.4.
Subsequently, a description will be given of a related-art PLL that extracts the synchronous clock from the reproduced RF signal. In the optical disc device, in order to enhance a read performance from the optical disc as much as possible, it is general to binalize the read RF signal by digital signal processing such as a partial response maximum likelihood (PRML) technique. To achieve this, there is a need to digitalize the RF signal by an analog to digital converter (ADC). The PLL also needs to be controlled so that a phase error of a sample string becomes minimized after digitalization. The sampling clock of the ADC is set as a frequency output of a frequency controllable local oscillator, and in order to accurately conduct phase comparison after ADC, processing is conducted by a high pass filter (HPF), and a phase error is generated from an output of the HPF by a phase comparator. The phase error is input to a digital loop filter to generate frequency information. The frequency information is converted into an analog signal by a digital to analog converter (DAC) to control an oscillation frequency of the local oscillator such as a voltage controlled oscillator (VCO). That is, a PLL loop where digital and analog signals are mixed together is formed. In the PLL, a loop delay between the ADC and the local oscillator output, such as conversion times of the ADC and the DAC, a response speed of the VCO, and an output delay due to the HPF is large, resulting in such a problem that the stability of the system is deteriorated when the loop gain is increased.
On the contrary, in order to minimize the loop delay of the PLL, there is a clock timing recovery system using digital information oversampled at a fixed frequency higher than the channel clock. For example, Japanese Patent Application Publication No. 2010-154083 discloses a related-art digital PLL. The digital PLL disclosed in Japanese Patent Application Publication No. 2010-154083 will be described with reference to FIG. 1. FIG. 1 is a block diagram illustrating a configuration of a related-art digital PLL circuit. After a signal output from an ADC 101 is processed by a filter 115 such as an HPF, the signal is subjected to rate conversion by an interpolator 102 to generate a phase error at the time of output from the interpolator 102 by a phase comparator (PC) 103. On the basis of the phase error, a loop filter (LPF) 104 generates frequency information, and controls the oscillating frequency of a numerical controlled oscillator (NCO) 106. The NCO 106 generates an interpolation phase Φ corresponding to the oscillating frequency, and controls the interpolator 102 to form a phase locked loop.
In the digital PLL of FIG. 1, because there is no conversion times of the ADC and the DAC and no input/output response time of the VCO, the loop delay can be reduced. Naturally, because the filter 115 is disposed outside the loop, there is no influence of the filter 115. Also, two sampling clock frequencies can be selected for an input channel rate so that a master clock frequency is not uselessly increased when the input signal is at a low channel rate (in particular, an inner periphery condition at the time of reproducing a CAV). There is provided a function for switching an input frequency value of the NCO 106 in a stepwise manner by a selector 111 and a multiplier 105 so that no frequency deviation of the synchronous clock occurs at the time of switching the master clock. The phase deviation at the time of switching the master clock is corrected by a first in first out (FIFO) memory 116 and a selector 117.
Likewise, as a configuration in which the PLL loop delay is minimized, and the sampling clock frequency is not increased even at the time of the low rate input, WO2008/129708 discloses a clock recovery system of the related art. The clock recovery system disclosed in WO2008/129708 will be described with reference to FIG. 2. FIG. 2 is a block diagram illustrating a configuration of a readout signal processing device including the digital PLL in the related art. The readout signal is oversampled by an ADC 202. A frequency ratio calculation unit 203 receives an output of the ADC 202, and calculates a frequency ratio of a readout signal channel clock and an output of a clock generator 201. On the basis of this result, a digital value generator 207 generates frequency information, and a DAC 211 controls a VCO 212, and an output of the VCO 212 becomes a sampling clock. That is, the sampling frequency is asynchronous with the channel clock, but the frequency ratio of the sampling clock and the channel clock is controlled to be constant. On the other hand, the output of the ADC 202 is also input to a phase correction amount calculation unit 204, and the phase correction amount calculation unit 204 generates a phase difference. A pseudo synchronous clock generator 205 receives the phase error, and generates a pseudo synchronous clock together with the phase information. This configuration is advantageous in that the PLL loop is configured by two stages to shorten the PLL loop delay while the ADC sampling clock frequency can be controlled with the degree of freedom higher than that of Japanese Patent Application Publication No. 2010-154083.